logic - VHDL gate basics -

I am learning VHDL and I have come to a stop. I want to make a simple door outside the small gates (a nand gate). Here's the code:

  Library IEEE; Use IEEE.STD_LOGIC_1164.all; The unit is the ANDGATE2 port (X, Y: STD_LOGIC; z: STD_LOGIC outside); End ANDGATE2; ANDGATE2 architecture begins ANDGATE2 z & lt; = X and y; End ANDGATE2; Library IEEE; Use IEEE.STD_LOGIC_1164.all; The unit is NOTGATE1 port (X: STD_LOGIC; z: STD_LOGIC outside); Termination Notate 1; NOTGATE1 of architecture NOTGATE1 starts at z < = NOT x; Termination Notate 1; Library IEEE; Use ieee.std_logic_1164.all; The institution is Nandgate 2 port (X: STD_LOGIC; Y: STD_LOGIC; z: STD_LOGIC outside); Closing ends 2; Nandgate 2 architecture Nandgat 2 signal C, D: studio_logic; Component NOTGATE1 port (n_in: STD_LOGIC; n_out: STD_LOGIC outside); End component; Component ANDGATE2 port (a_in1, a_in2: STD_LOGIC; a_out: STD_LOGIC out); End component; Start N0: ANDGATE2 Port Map (X, Y, C); N1: Notgate 1 Port Map (C, D); Z & lt; = D; Closing ends 2;   
 Here are the code from some tutorials that I am using as a template; That is not a problem.  
  library ieee; Use ieee.std_logic_1164.all; - Definition of a complete connector unit is FULLADDER port (A, B, C: std_logic; yoga, le: outside std_logic); End of FULLADDER; The fundamentals of the Fuldair architecture Fuldder_Behve begin & lt; = (A xor b) xor c; Take & lt; = (A and b) or (c and (a xor b)); Completely sound; IEEE 4-bit additives library; Use ieee.std_logic_1164.all; Unit four BITADD port (A, B: std_logic_vector (down to 3); Cin: std_logic; sum: out std_logic_vector (3 down from 0); Cout, V: out std_logic); Fourth BITDA; The structure of the architectural four-edder is four BITADD signals c: std_logic_vector (4 downto 0); Component FoederEd port (A, B, C: stud_logic; yoga, move: std_logic outside); End component; Start the FA0: Fuldair port map (A (0), B (0), cine, zodiac (0), c (1)); FA1: FullDonder Port Map (A (1), B (1), C (1), Zodiac (1), C (2)); FA2: Fuldeider Port Map (A (2), B (2), C (2), Zodiac (2), C (3)); FA3: Fuldiere Port Map (A (3), B (3), C (3), Amount (3), C (4)); V & LT; = C (3) Excerpt C (4); Cot & lt; = C (4); Eventually the structure of fourteen;   
 There is no error in my code, but with two warnings:  
  # Warning: ELAB1_0026: p2.vhd: (85, 0) : No default restriction for component "andgate2" (Port is not on "a_in1" unit) # Warning: ELAB1_0026: p2.vhd: (87, 0): There is no default binding for component "notgate1". (Port is not on "N_इन" unit)   
 What gives?   
 
 
 You must use the same port name on your components and unit announcements.  
 For now, for example in your  NOTGATE1  unit declaration, you have input port  x  and output port  Z  but In the  Nandgate 2  architecture, you can 
 port  n_in  and  n_out  to  NOTGATE1  component.  
 This will not cause problems during the compilation, since the compilation sees one unit at a time, and real entities will not be visible. In the expansion phase, your device will try to match the entities with components, but it will fail because the ports are not closed.