gnu make - A Concise Makefile -

I'm refactoring some Makefile and trying to learn the shortest way to implement a makefile that does the following

1. is a variable in which all source files are listed (both C and C ++ files can be)
2. All the object files are generated in OBJDiIR < / Li>
3. The object becomes a directory if it does not exist

   Here is what I Has done so far:

     ... OBJ_DIR = obj / bin_DIR = bin / program = Programs SRCS = test1.cpp test2.c objs = $ (adbfx $ (objdir), \ $ (Patsubst% .cpp,% .o, \ $ (patsubst% .c,% .o, $ (SRCS))) $ (BIN_DIR) $ (program): $ (objs) $ (CREATE_OUT_DIR) $ (LINK) $ (Objdir)% O:%. C $ (CREATE_OBJ_DIR) $ (ccomil) $ (objdir)% O:% CPP $ (CREATE_OBJ_DIR) $ (CPPCOMPILE) ...   
    I want to end the call for $ (CREATE_OBJ_DIR) each. Compile it. Anyone know how to do this? I tried to add it, but then it will not create the object files:  
     $ (oBJS): | $ (OBJDIR) $ (OBJDIR): $ (CREATE_OBJ_DIR)    
    
    
    You already have Resolved your first point: keep them all in one variable (I do not think you actually have to separate them TEMP1 and TEMP2 as you have, just different rules)  
    For the second point, you can tell the compiler to output the object files (like this for G ++:  
     g ++ -c MySourceFile.cpp -o obj / MySourceFile.o   
    this Will make rules for:  
     obj /%. O:% .cpp g ++ -c $ *. Cpp-o obj / $ * .o   < P> And your third point is also easily solved, because you can make a rule for it (just before all of the objects are listed, enter the directory name in the dependency list for the target), and the build rule Edit: Or follow the example of your code:  
     $ ( BINIDIR) $ (Pro Ram): $ (Biaianaidiaiar) $ (Obijes) $ (link) $ (B IN_DIR): $ (CREATE_OUT_DIR)