I have the original 8-bit ALU as described in Verilog. I'm trying to implement the design, but I'm getting the error message:
Error: NgdBuild: 809 - Output Pad Net 'quotient & lt; 1> An illegal loading is: Block MMUX_PoClick [2] _GND_1_o_wide_mux_8_OUT81 Pin I3 type LUT6 with type
The design follows the following operations, addition, subtraction, multiplication, division, and, or, XOR, and XNOR. The interesting thing about this is that Xilinx XST can not synthesize a divider unless the dividend is being divided by a component of 2 (basically correct move). So take care of this I used a core IP component generated by the Xilinx core generator. It takes a clock (no clock is capable or synchronous, and gives approximately the right quotient and the remaining output after about 20 or so of the clock. The core can be found only under the mathematical functions in the core generator program. , Here is my code: Obviously my code is terrible and my comments are probably wrong, but I'm just starting with Verlog. However, I plan to add more operations for me to improve and practice this code. The module itself synthesizes successfully and imitates correctly, but I am unable to apply it to any FPGA. Does anyone know that the code, or Xilinx is a problem with the ISE (which is normally full of bugs), or maybe the project settings? EDIT: I have made some changes to the code, to reflect the advice provided by the answer. Do you have the "Create netlist cover with IO Pad" option selected in your Korgan project? By error it seems that dividers are OBUF or similar output buffers in 8 cores, which run output output. OBUF can only run the signal which is leaving the FPGA. Another note, although it is not related to NGDBild error: Generally non-intercepted work sequential blocks ("always @"), such as "out and lieutenant; = A + B" It is that until all other incidents are not processed at the present time, it avoids running conditions in the signal. `TIMESIL 1ns / 1ps module ALU8 (A, B, opcode, clk, OUT); // I / O // We have 16 bit input input [ 7: 0] A, B; // Opps our next operation input [2: 0] opcode; // Processor clock input clique; // 32-bit Output output [15: 0] Output // wires wire wire [7: 0] A, B, wire [2: 0] OPOD; // Output is a register reg [15: 0] OAT; // Tie dividers wire For quotient and balance, [7: 0] quotient, balance; // Divider8 divider divider (.rfd (), .clk (clk), .dividend (A), .quotient (fraction), .divisor (B), .fractional (remaining)); // defined operation code, only 9 parameters ADD = 3'b 2000 parameter SUB = 3'b001; parameter MUL = 3'b010; parameter DIV = 3'b011; parameter and = 3 'B100; parameter OR = 3'b101; parameter XOR = 3'b110; parameter XNOR = 3'b111; // always starting @ (Pozgade CLK) on the rising edge of the clock / / the output is determined by the operation. // it will be added in the latter case as the MUX / A MUX 8 (OPOD) Add: Out & Lt; = A + B; Sub: Out & lt; = A - B; MUL: Outside & lt; = A * B; DIV: outside and lieutenant; = {Quotient, balance}; And: Out and Lieutenant; = A & amp; B; Or: out and lieutenant; = A | B; XOR: Out and LT; = A ^ b; XNOR: Out and Lieutenant; = A ~ B; Default: Out & lt; = 16'b0000000000000000; AndCand and Endmodule
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